This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-278254, filed Sep. 30, 1999; and No. 11-280046, filed Sep. 30, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device with a trench gate, such as an insulated-gate-type transistor (IGBT (Insulated Gate Bipolar Transistor)).
In an insulated-gate-type semiconductor device such as an IGBT, the conduction loss can be reduced by a buried trench gate. This is because forming a fine trench gate increases the channel density, and forming a deep trench gate promotes conductivity modulation.
FIGS. 20A and 20B are sectional and plan views, respectively, showing a conventional IGBT with a trench gate. FIG. 20A shows a section taken along a line XXAxe2x80x94XXA in FIG. 20B.
In this IGBT, a p-base layer 102 is formed on an n-base layer 101. A plurality of trenches 103 having a stripe structure are formed to extend through the p-base layer 102 and reach the n-base layer 101. In each trench 103, a gate electrode 104 is buried via a gate insulating film 111 formed on the sidewall and bottom surface. An n-emitter layer 105 is formed in the p-base layer 102 to come into contact with the trench 103.
An insulating film 108 is selectively formed on the p-base layer 102, n-emitter layers 105, and trenches 103. An emitter electrode 109 is formed on the insulating film 108 and comes into contact with the n-emitter layer 105 and p-base layer 102 through contact holes. A p-emitter layer 107 is formed on the opposite-side surface of the n-base layer 101 via an n-buffer layer 106. A collector electrode 110 is further formed in contact with the p-emitter layer 107.
To operate this IGBT, a positive bias is applied across the collector electrode 110 and emitter electrode 109, and in this state, a positive bias is applied to the gate electrode 104. At this time, an inversion layer is formed in the p-base layer 102 along the surface of the gate insulating film 111, and electrons are injected from the n-emitter layer 105 into the n-base layer 101. On the other hand, holes are injected from the p-emitter layer 107 into the n-base layer 101 in correspondence with the injected electron amount. As the n-base layer 101 is filled with carriers, conductivity modulation occurs. For this reason, the resistance of the n-base layer 101 decreases to turn on the device.
In the IGBT shown in FIGS. 20A and 20B, one factor that determines the conduction loss in the ON state is the resistance of the n-base layer 101 when conductivity modulation has occurred. The resistance of the n-base layer 101 depends on the total amount of carriers that fill this layer. The total amount of carriers is determined by the ratio of an electron current to a hole current, flowing from the n-base layer 101 to the p-base layer 102. As the distance between the trenches 103, which determines the width of a current path region 131 connected to the emitter electrode 109, decreases, the resistance in flow of the holes to the emitter electrode 109 through the p-base layer 102 increases. For this reason, the amount of carriers filling the n-base layer 101 increases, and the conduction loss decreases.
However, when the distance between the trenches 103 decreases, the alignment margin between a trench formation mask and a contact formation mask decreases, and the number of defects increases in the manufacturing process, resulting in low yield. To ensure the minimum necessary mask alignment margin, the distance between the trenches 103 cannot be reduced excessively. That is, since the distance between the trenches 103 cannot be reduced below a given value, the hole flow resistance cannot be increased on the basis only of a decreasing in this distance.
In the IGBT shown in FIGS. 20A and 20B, the other factor that determines the conduction loss in the ON state is the resistance of a channel induced by the gate electrode 104. The channel resistance can be lowered by increasing the area of a region where the channel is induced, i.e., by increasing the density in the channel region. However, when the distance between the trenches 103 is determined, the density of the p-base layer 102 also increases with increasing channel density. That is, the decrease in channel resistance and promotion of conductivity modulation have tradeoff relationships, and therefore, the conduction loss can be decreased only to a limited level.
Devices with a large current capacity are generally used in parallel connection. In the conventional structure, however, since trench gates are formed at a high density, the electrostatic capacitance between a gate electrode and a main electrode (collector electrode or emitter electrode) becomes large. This electrostatic capacitance causes delay or nonuniformity in switching operation or generates parasitic oscillation.
In the IGBT shown in FIGS. 20A and 20B, since the gate-collector capacitance acts as a mirror capacitance in turning off, a period (to be referred to as a mirror period hereinafter) when a predetermined potential difference is held between the gate and the emitter is generated. If the mirror period is long, the energy loss in turning off is large because the energy loss is in proportion to the turn-off time. In addition, during the mirror period, the potential is unstable, and a current readily concentrates in a large-size device or in parallel operation of devices, resulting in lower controllable current of the device.
Hence, the characteristics of the semiconductor device can be improved by shortening the mirror period. However, in the conventional IGBT with a trench gate, a non-current path region 132 which is not connected to the emitter electrode 109 contributes to the gate-collector capacitance. As a consequence, the gate-collector capacitance increases, and the mirror period becomes long.
It is an object of the present invention to provide a semiconductor device with a trench gate, which can increase the hole flow resistance without reducing the distance between trenches and decrease the conduction loss.
It is another object of the present invention to provide a semiconductor device with a trench gate, which can reduce the gate-collector capacitance without increasing the conduction loss.
It is still another object of the present invention to provide a semiconductor device with a trench gate, which can reduce the conduction loss beyond the limit of a prior-art device (increase the channel density and promote conductivity modulation) and also facilitate parallel connection.
According to the first aspect of the present invention, there is provided a semiconductor device with a trench gate, comprising:
a first semiconductor layer of first conductivity type;
a second semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to inject carriers of second conductivity type into the first semiconductor layer;
a third semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to collect the carriers of second conductivity type in the first semiconductor layer from the first semiconductor layer;
a pair of trench portions extending through the third semiconductor layer and reaching the first semiconductor layer;
a pair of gate electrode portions disposed in the pair of trench portions via gate insulating films, respectively;
a pair of fourth semiconductor layer portions of first conductivity type, which are formed along the pair of trench portions, respectively, in a surface portion of the third semiconductor layer interposed between the pair of trench portions, each of the fourth semiconductor layer portions being arranged to inject carriers of first conductivity type through a channel induced in the third semiconductor layer by the gate electrode portion into the first semiconductor layer and cause conductivity modulation therein;
a first main electrode disposed in contact with the second semiconductor layer;
a second main electrode disposed in contact with the third semiconductor layer and fourth semiconductor layer portions; and
a narrowing trench formed between the pair of fourth semiconductor layer portions to extend through the third semiconductor layer and reach the first semiconductor layer, and to narrow a flow path of the carrier of second conductivity type, which is formed from the first semiconductor layer to the second main electrode through the third semiconductor layer.
According to the second aspect of the present invention, there is provided a semiconductor device with a trench gate, comprising:
a first semiconductor layer of first conductivity type;
a second semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to inject carriers of second conductivity type into the first semiconductor layer;
a third semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to collect the carriers of second conductivity type in the first semiconductor layer from the first semiconductor layer;
a pair of trench portions extending through the third semiconductor layer and reaching the first semiconductor layer;
a pair of gate electrode portions disposed in the pair of trench portions via gate insulating films, respectively;
a pair of fourth semiconductor layer portions of first conductivity type, which are formed along the pair of trench portions, respectively, in a surface portion of the third semiconductor layer which is not interposed between the pair of trench portions, each of the fourth semiconductor layer portions being arranged to inject carriers of first conductivity type through a channel induced in the third semiconductor layer by the gate electrode portion into the first semiconductor layer and cause conductivity modulation therein;
a first main electrode disposed in contact with the second semiconductor layer;
a second main electrode disposed in contact with the third semiconductor layer and fourth semiconductor layer portions; and
an isolation insulating layer formed between the pair of trench portions to isolate, from the first semiconductor layer, a semiconductor layer in a non-current path region interposed between the pair of trench portions.
According to the third aspect of the present invention, there is provided a semiconductor device with a trench gate, comprising:
a first semiconductor layer of first conductivity type;
a second semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to inject carriers of second conductivity type into the first semiconductor layer;
a third semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to collect the carriers of second conductivity type in the first semiconductor layer from the first semiconductor layer;
a pair of trench portions extending through the third semiconductor layer and reaching the first semiconductor layer;
a pair of gate electrode portions disposed in the pair of trench portions via gate insulating films, respectively;
a pair of fourth semiconductor layer portions of first conductivity type, which are formed along the pair of trench portions, respectively, in a surface portion of the third semiconductor layer which is not interposed between the pair of trench portions, each of the fourth semiconductor layer portions being arranged to inject carriers of first conductivity type through a channel induced in the third semiconductor layer by the gate electrode portion into the first semiconductor layer and cause conductivity modulation therein;
a first main electrode disposed in contact with the second semiconductor layer;
a second main electrode disposed in contact with the third semiconductor layer and fourth semiconductor layer portions; and
a fifth semiconductor layer of second conductivity type, which is formed in a non-current path region interposed between the pair of trench portions and has a resistance lower than that of the third semiconductor layer.
According to the fourth aspect of the present invention, there is provided a semiconductor device with a trench gate, comprising:
a first semiconductor layer of first conductivity type;
a second semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to inject carriers of second conductivity type into the first semiconductor layer;
a third semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to collect the carriers of second conductivity type in the first semiconductor layer from the first semiconductor layer;
a plurality of main trench portions extending in a first direction along a surface of the third semiconductor layer, and extending through the third semiconductor layer and reaching the first semiconductor layer in a depth direction;
a plurality of cross trench portions extending in a second direction perpendicular to the first direction along the surface of the third semiconductor layer in columns between the main trench portions, and extending through the third semiconductor layer and reaching the first semiconductor layer in a depth direction, the cross trench portions being arranged such that the columns include a column having the cross trench portions and a column having no cross trench portions;
a gate electrode disposed in each of the main and cross trench portions via a gate insulating film;
fourth semiconductor layer portions of first conductivity type, each of which is formed along the main and cross trench portions while leaving a central exposed portion of the third semiconductor layer in a surface portion of the third semiconductor layer surrounded by the main and cross trench portions, each of the fourth semiconductor layer portions being arranged to inject carriers of first conductivity type through a channel induced in the third semiconductor layer by the gate electrode into the first semiconductor layer and cause conductivity modulation therein;
a first main electrode disposed in contact with the second semiconductor layer; and
a second main electrode disposed in contact with the central exposed portion of the third semiconductor layer and the fourth semiconductor layer portions.
According to the first aspect of the present invention, a semiconductor device with a trench gate is provided by forming a narrowing trench in the current path region, so that the device can increase the hole flow resistance without reducing the distance between trenches and decrease the conduction loss.
According to the second and third aspects of the present invention, a semiconductor device with a trench gate is provided by insulating and isolating the non-current path region at least in the OFF state, so that the device can reduce the gate-collector capacitance without increasing the conduction loss.
According to the fourth aspect of the present invention, a semiconductor device with a trench gate is provided by employing a ladder-shaped trench gate, so that the device can realize both the increase in channel density and promotion of conductivity modulation. Additionally, with this effect, since the interval between two ladder-shaped gate electrodes can be made large to reduce the parasitic electrostatic capacitance between the gate electrode and the main electrode, a semiconductor device with a trench gate which facilitates parallel connection can be provided.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.